PIC16C54C-04I/SO【PDF 51/194 页】IC MCU OTP 512X12 18SOIC

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PIC18F2450/4450

DS39760A-page 142

Advance Information

2006 Microchip Technology Inc.

TABLE 14-4:

ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT

BUFFERING MODES

TABLE 14-5:

SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Endpoint

BDs Assigned to Endpoint

Mode 0

(No Ping-Pong)

Mode 1

(Ping-Pong on EP0 OUT)

Mode 2

(Ping-Pong on all EPs)

Out

0 (E), 1 (O)

2 (E), 3 (O)

4 (E), 5 (O)

6 (E), 7 (O)

8 (E), 9 (O)

10 (E), 11 (O)

12 (E), 13 (O)

14 (E), 15 (O)

16 (E), 17 (O)

18 (E), 19 (O)

20 (E), 21 (O)

22 (E), 23 (O)

24 (E), 25 (O)

26 (E), 27 (O)

28 (E), 29 (O)

30 (E), 31 (O)

32 (E), 33 (O)

34 (E), 35 (O)

36 (E), 37 (O)

38 (E), 39 (O)

40 (E), 41 (O)

42 (E), 43 (O)

44 (E), 45 (O)

46 (E), 47 (O)

48 (E), 49 (O)

50 (E), 51 (O)

52 (E), 53 (O)

54 (E), 55 (O)

56 (E), 57 (O)

58 (E), 59 (O)

60 (E), 61 (O)

62 (E), 63 (O)

Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BDnSTAT(1)

UOWN

DTS(4)

PID3(2)

PID2(2)

PID1(2)

DTSEN(3)

PID0(2)

BSTALL(3)

BC9

BC8

BDnCNT(1)

Byte Count

BDnADRL(1)

Buffer Address Low

BDnADRH(1)

Buffer Address High

Note 1:

For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are

shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).

Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register

is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values

written for DTSEN and BSTALL are no longer valid.

Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 3 and 2 of the BDnSTAT

This bit is ignored unless DTSEN = 1.

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